ports_def.h

00001 /* m68hc12/ports_def.h -- Definition of 68HC12 ports
00002    Copyright 1999, 2000 Free Software Foundation, Inc.
00003    Written by Stephane Carrez (stcarrez@worldnet.fr)
00004 
00005    - Jul 2003 Modified by Jefferson Smith, Robotronics Corp.
00006      Ported to work with m68hc12, and some backwards compatible
00007      definitions.
00008 
00009 This file is part of GDB, GAS, and the GNU binutils.
00010 
00011 GDB, GAS, and the GNU binutils are free software; you can redistribute
00012 them and/or modify them under the terms of the GNU General Public
00013 License as published by the Free Software Foundation; either version
00014 1, or (at your option) any later version.
00015 
00016 GDB, GAS, and the GNU binutils are distributed in the hope that they
00017 will be useful, but WITHOUT ANY WARRANTY; without even the implied
00018 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
00019 the GNU General Public License for more details.
00020 
00021 You should have received a copy of the GNU General Public License
00022 along with this file; see the file COPYING.  If not, write to the Free
00023 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
00024 
00025 #ifndef _M68HC12_PORTS_DEF_H
00026 #define _M68HC12_PORTS_DEF_H
00027 
00028 typedef unsigned char byte;
00029 
00030 /* Flags for the definition of the 68HC11 & 68HC12 CCR.  */
00031 #define M6811_S_BIT     0x80    /* Stop disable */
00032 #define M6811_X_BIT     0x40    /* X-interrupt mask */
00033 #define M6811_H_BIT     0x20    /* Half carry flag */
00034 #define M6811_I_BIT     0x10    /* I-interrupt mask */
00035 #define M6811_N_BIT     0x08    /* Negative */
00036 #define M6811_Z_BIT     0x04    /* Zero */
00037 #define M6811_V_BIT     0x02    /* Overflow */
00038 #define M6811_C_BIT     0x01    /* Carry */
00039 /* equivalents without the M68HC11 indication, because it is the
00040    same for M68HC12. */
00041 #define CC_S     (byte)(1<<7)          //Stop disable
00042 #define CC_X     (1<<6)          //X-interrupt mask
00043 #define CC_H     (1<<5)          //Half carry flag
00044 #define CC_I     (1<<4)          //I-interrupt mask
00045 #define CC_N     (1<<3)          //Negative
00046 #define CC_Z     (1<<2)          //Zero
00047 #define CC_V     (1<<1)          //Overflow
00048 #define CC_C     1             //Carry
00049 
00050 /* 68HC11 register names which are forward compatible enough to simply 
00051    change the address offsets.
00052 
00053 */
00054 #define M6811_PORTA     0x00    /* Port A register */
00055 #define M6811_PORTB     0x01    /* Port B register */
00056 
00057 #define M6811_TCTN      0x84    /* Timer Counter Register */
00058 
00059 
00060 /* 68HC12 register names
00061    addresses to registers for hc12 to be added to _io_ports base 
00062    address. 
00063 */
00064 #define M6812_PORTA     0x00       //Port A register
00065 #define M6812_PORTB     0x01       //Port B register
00066 #define M6812_DDRA      0x02       //Data Direction Port A
00067 #define M6812_DDRB      0x03       //Data Direction Port A
00068 #define M6812__RES4     0x04
00069 #define M6812__RES5     0x05
00070 #define M6812__RES6     0x06
00071 #define M6812__RES7     0x07
00072 #define M6812_PORTE     0x08    //Port E register
00073 #define M6812_DDRE      0x09    //DAta Direction Port E
00074 
00075 #define M6812_PEAR      0x0A
00076 /* Flags in PEAR */
00077 #define M6812_NDBE      (byte)(1<<7)
00078 #define M6812_CGMTE     (1<<6)
00079 #define M6812_PIPOE     (1<<5)
00080 #define M6812_NECLK     (1<<4)
00081 #define M6812_LSTRE     (1<<3)
00082 #define M6812_RDWE      (1<<2)
00083 
00084 #define M6812_MODE      0x0B    //Mode control
00085 /* Flags in MODE register */
00086 #define M6812_SMODN     (byte)(1<<7)
00087 #define M6812_MODB      (1<<6)
00088 #define M6812_MODA      (1<<5)
00089 #define M6812_ESTR      (1<<4)
00090 #define M6812_IVIS      (1<<3)
00091 #define M6812_EBSWAI    (1<<2)
00092 #define M6812_EME       (1<<0)
00093 #define M6812_EXPA_NARROW (M6812_MODA|M6812_ESTR)             //0x30
00094 #define M6812_EXPA_WIDE   (M6812_MODB|M6812_MODA|M6812_ESTR)  //0x70
00095 
00096 #define M6812_PUCR      0x0C    //Pullup Resistor Control reg
00097 /* Flags in PUCR register */
00098 #define M6812_PUPE      (1<<4)   //port E inputs (PE1 always, PE6-4 never)
00099 #define M6812_PUPB      (1<<1)   //except in external bus mode
00100 #define M6812_PUPA      (1<<0)
00101 
00102 #define M6812_RDRIV     0x0D    //Reduced Driver Register
00103 #define M6812__RESE     0x0E
00104 #define M6812__RESF     0x0F
00105 
00106 #define M6812_INITRM    0x10    //Ram mapping
00107 /* Field in INITRM */
00108 #define M6812_POS_RMMAP 3
00109 #define M6812_MSK_RMMAP (0x1F<<M6812_POS_RMMAP)
00110 
00111 #define M6812_INITRG    0x11    //Register mapping
00112 
00113 #define M6812_INITEE    0x12    //Eeprom mapping
00114 /* Flags/Fields in INITEE */
00115 #define M6812_POS_EEMAP 4
00116 #define M6812_MSK_EEMAP (0xF<<M6812_POS_EEMAP)
00117 #define M6812_EEON      (1<<0)
00118 
00119 #define M6812_MISC      0x13
00120 /* Flags/Fields in MISC */
00121 #define M6812_NDRF      (1<<6)                     //narrow buss in reg-follow
00122 #define M6812_POS_RFSTR  4                         //reg-follow space stretch
00123 #define M6812_MSK_RFSTR (0x3<<M6812_POS_RFSTR)
00124 #define M6812_POS_EXSTR  2                         //external space strech
00125 #define M6812_MSK_EXSTR (0x3<<M6812_POS_EXSTR)
00126 #define M6812_MAPROM    (1<<1)                     //map rom location
00127 #define M6812_ROMON     (1<<0)                     //rom enable
00128 
00129 #define M6812_RTICTL    0x14
00130 /* Flags in RTICTL */
00131 #define M6812_RTIE   (byte)(1<<7)
00132 #define M6812_RSWAI     (1<<6)
00133 #define M6812_RSBCK     (1<<5)
00134 #define M6812_RTBYP     (1<<3)
00135 #define M6812_MSK_RTR    (0x7)
00136 
00137 #define M6812_RTIFLG    0x15
00138 /* Flag in RTIFLG */
00139 #define M6812_RTIF      0x80
00140 
00141 #define M6812_COPCTL    0x16    //COP control register
00142 /* Flags in COPCTL */
00143 #define M6812_CME     (byte)(1<<7)  //Clock Monitor Enable
00144 #define M6812_FCME      (1<<6)  //Force Clock Monitor Enable (overrides CME)
00145 #define M6812_FCM       (1<<5)  //special Force Clock Monitor Reset
00146 #define M6812_FCOP      (1<<4)  //special Force COP Reset
00147 #define M6812_DISR      (1<<3)  //special timeout disable
00148 #define M6812_MSK_CR    (0x7)   //mask for COP Reset
00149 
00150 #define M6812_COPRST    0x17    //COP reset register
00151 #define M6812_ITST0     0x18
00152 #define M6812_ITST1     0x19
00153 #define M6812_ITST2     0x1A
00154 #define M6812_ITST3     0x1B
00155 #define M6812__RES1C    0x1C
00156 #define M6812__RES1D    0x1D
00157 #define M6812_INTCR     0x1E
00158 #define M6812_HPRIO     0x1F
00159 #define M6812_BRKCT0    0x20
00160 #define M6812_BRKCT1    0x21
00161 #define M6812_BRKAH     0x22
00162 #define M6812_BRKAL     0x23
00163 #define M6812_BRKDH     0x24
00164 #define M6812_BRKDL     0x25
00165 /*           0x26 - 0x3F  Reserved (from HC11?)
00166 */
00167 #define M6812_PWCLK     0x40
00168 /* Flags in PWCLK */
00169 #define M6812_CON23     (byte)(1<<7)             //concat PWM 2 and 3
00170 #define M6812_CON01     (1<<6)             //concat     0 and 1
00171  //5-3  clk A prescale n as in: Eclk / 2^n
00172  //2-0  clk B prescale n
00173 
00174 #define M6812_PWPOL     0x41
00175 /* Flags in PWPOL */
00176 #define M6812_PCLK3     (byte)(1<<7)             //1= Clock S1 instead of B
00177 #define M6812_PCLK2     (1<<6)             //1= Clock S1 instead of B
00178 #define M6812_PCLK1     (1<<5)             //1= Clock S0 instead of A
00179 #define M6812_PCLK0     (1<<4)             //1= Clock S0 instead of A
00180 #define M6812_PPOL3     (1<<3)             //1=duty high
00181 #define M6812_PPOL2     (1<<2)
00182 #define M6812_PPOL1     (1<<1)
00183 #define M6812_PPOL0     (1<<0)
00184 
00185 #define M6812_PWEN      0x42             //enable PWM outputs
00186 /* Flags in PWEN */
00187 #define M6812_PWEN3     (1<<3)
00188 #define M6812_PWEN2     (1<<2)
00189 #define M6812_PWEN1     (1<<1)
00190 #define M6812_PWEN0     (1<<0)
00191 
00192 #define M6812_PWPRES         0x43
00193 #define M6812_PWSCAL0        0x44             // clk S0 prescale n: clkA/(n+1)/2
00194 #define M6812_PWSCNT0        0x45
00195 #define M6812_PWSCAL1        0x46             // clk S1 prescale n: clkB/(n+1)/2
00196 #define M6812_PWSCNT1        0x47
00197 #define M6812_PWCNT0         0x48             //counter for a running PWM
00198 #define M6812_PWCNT1         0x49
00199 #define M6812_PWCNT2         0x4A
00200 #define M6812_PWCNT3         0x4B
00201 #define M6812_PWPER0         0x4C             //period (controls freq)
00202 #define M6812_PWPER1         0x4D
00203 #define M6812_PWPER2         0x4E
00204 #define M6812_PWPER3         0x4F
00205 #define M6812_PWDTY0         0x50             //duty (controls pulse width)
00206 #define M6812_PWDTY1         0x51
00207 #define M6812_PWDTY2         0x52
00208 #define M6812_PWDTY3         0x53
00209 
00210 #define M6812_PWCTL          0x54
00211 /* Flags in PWCTL */
00212 #define M6812_PSWAI          (1<<4)           //Halt in wait mode
00213 #define M6812_CENTR          (1<<3)           //Center-aligned output mode
00214 #define M6812_RDPP           (1<<2)           //Reduced drive all outputs
00215 #define M6812_PUPP           (1<<1)           //pullups on all inputs
00216 #define M6812_PSBCK          (1<<0)           //stop in Bgnd debug mode
00217 
00218 #define M6812_PWTST          0x55
00219 #define M6812_PORTP          0x56
00220 #define M6812_DDRP           0x57
00221 
00222 #define M6812_ATDCTL0        0x60             //Abort AD sequence when write
00223 #define M6812_ATDCTL1        0x61             //special mode use
00224 
00225 #define M6812_ATDCTL2        0x62
00226 /* Flags in ATDCTL2 reg (enable AD, etc) */
00227 #define M6812_ADPU     (byte)(1<<7)         // Power up (enable)
00228 #define M6812_AFFC     (1<<6)         // fast reset (just read data)
00229 #define M6812_AWAI     (1<<5)         // Stop in Wait
00230 #define M6812_ASCIE    (1<<1)         // AD sequence complete interrup enable
00231 #define M6812_ASCIF     1            // AD sequence complete interrup flag
00232 
00233 #define M6812_ATDCTL3   0x63
00234 /* Modes in ATDCTL3 reg (BDM freeze modes) */
00235 #define M6812_FRZ_NONE   0x00      // run normal while stopped in BDM
00236 #define M6812_FRZ_FINISH 0x02      // finish current conv then freeze
00237 #define M6812_FRZ_IMM    0x03      // freeze while in BDM
00238 
00239 #define M6812_ATDCTL4   0x64
00240 /* Flags/modes in ATDCTL4 reg (8/10 bits, conversion speed) */
00241 #define M6812_S10BM       (byte)(1<<7)     //10 bit AD
00242 #define M6812_POS_SMP    5
00243 #define M6812_MSK_SMP    (byte)(0x3<<M6812_POS_SMP)
00244  // SMP values by final sample cycles. SMP16 is most stable conversion time(?)
00245 #define M6812_SMP2             0
00246 #define M6812_SMP4       (byte)(0x1<<M6812_POS_SMP)
00247 #define M6812_SMP8       (byte)(0x2<<M6812_POS_SMP)
00248 #define M6812_SMP16      (byte)(0x3<<M6812_POS_SMP)
00249                                    // prescale 00001 (div 4) is default
00250 
00251 #define M6812_ATDCTL5   0x65
00252 /* Flags/modes in ATDCTL5 reg (write starts conv. select modes, channels) */
00253 #define M6812_S8CM       (byte)(1<<6)      //read sequence of 4 or 8
00254 #define M6812_SCAN       (byte)(1<<5)      // whether to scan repeatedly
00255 #define M6812_MULT       (byte)(1<<4)      //read 1, or sequence of 4/8
00256 
00257 #define M6812_ATDSTAT  0x66
00258 #define M6812_ATDSTAT0 0x66
00259 /* Flags/fields in ATDSTAT0 */
00260 #define M6812_SCF        (byte)(1<<7)      //Sequence Complete Flag
00261 #define M6812_MSK_CC     0x7               //Conversion Counter
00262 
00263 #define M6812_ATDSTAT1 0x67                //CCF7-0
00264 #define M6812_ATDTESTH 0x68
00265 #define M6812_ATDTESTL 0x69
00266 
00267 #define M6812_PORTAD0  0x6F
00268 #define M6812_ADR00    0x70
00269 #define M6812_ADR00L   0x71
00270 #define M6812_ADR01    0x72
00271 #define M6812_ADR01L   0x73
00272 #define M6812_ADR02    0x74
00273 #define M6812_ADR02L   0x75
00274 #define M6812_ADR03    0x76
00275 #define M6812_ADR03L   0x77
00276 #define M6812_ADR04    0x78
00277 #define M6812_ADR04L   0x79
00278 #define M6812_ADR05    0x7A
00279 #define M6812_ADR05L   0x7B
00280 #define M6812_ADR06    0x7C
00281 #define M6812_ADR06L   0x7D
00282 #define M6812_ADR07    0x7E
00283 #define M6812_ADR07L   0x7F
00284 
00285 #define M6812_TIOS      0x80                    //Timer IC/OC select
00286 #define M6812_CFORC     0x81                    //Timer Compare Force
00287 #define M6812_OC7M      0x82                    //Output Compare 7 Mask
00288 #define M6812_OC7D      0x83                    //Output Compare 7 Data
00289 #define M6812_TCNT      0x84                    //Hardware Timer Count
00290 
00291 #define M6812_TSCR      0x86                    //Timer system control
00292 /* Flags in TSCR register */
00293 #define M6812_TEN     (byte)(1<<7)         //Timer Enable
00294 #define M6812_TSWAI   (byte)(1<<6)         //Timer Stops While in Wait
00295 #define M6812_TSBCK   (byte)(1<<5)         //Timer Stops in Background Mode
00296 #define M6812_TFFCA   (byte)(1<<4)         //Timer Fast Flag Clear All
00297 
00298 #define M6812_TQCR      0x87            //**Reserved**
00299 
00300 #define M6812_TCTL1     0x88                    //Timer Control 1
00301 #define M6812_TCTL2     0x89                    //Timer Control 2
00302 /* Modes for bit pairs in TCTL1-2 */
00303 #define M6812_TOC_NONE    0x0     //No output for this timer
00304 #define M6812_TOC_TOGGLE  0x1     //Toggle output pin on compare
00305 #define M6812_TOC_CLEAR   0x2     //Clear output pin on compare
00306 #define M6812_TOC_SET     0x3     //Set output pin on compare
00307 
00308 #define M6812_TCTL3     0x8A
00309 #define M6812_TCTL4     0x8B
00310 /* Modes for bit pairs in TCTL3-4 */
00311 #define M6812_TIC_NONE    0x0     //No edge detected
00312 #define M6812_TIC_RISE    0x1     //detect rising edge
00313 #define M6812_TIC_FALL    0x2     //detect falling edge
00314 #define M6812_TIC_BOTH    0x3     //detect both edges
00315 
00316 #define M6812_TMSK1     0x8C      //enable interrupt for each timer 0-7
00317 
00318 #define M6812_TMSK2     0x8D
00319 /* Flags in TMSK2 (over flow I, pullups, reduce drv, oc7 timer reset) */
00320 #define M6812_TOI         (byte)(1<<7)     //ena timer overflow interrupt
00321 #define M6812_PUPT        (byte)(1<<5)     //ena pullup resistors on inputs
00322 #define M6812_RDPT        (byte)(1<<4)     //reduced drive outputs
00323 #define M6812_TCRE        (byte)(1<<3)     //reset TCNT on oc7 compare
00324 #define M6812_MSK_PR      0x07             //prescale divider*2
00325 
00326 #define M6812_TFLG1     0x8E             //TC flags (timer compare/capture 0-7)
00327 #define M6812_TFLG2     0x8F
00328 /* Flags in M6812_TFLG2 could check if whole byte=0 since all other bytes always 0 */
00329 #define M6812_TOF         (byte)(1<<7)     //timer over flow flag
00330 
00331 #define M6812_TC0       0x90
00332 #define M6812_TC1       0x92
00333 #define M6812_TC2       0x94
00334 #define M6812_TC3       0x96
00335 #define M6812_TC4       0x98
00336 #define M6812_TC5       0x9A
00337 #define M6812_TC6       0x9C
00338 #define M6812_TC7       0x9E
00339 #define M6812_PACTL     0xA0
00340 #define M6812_PAFLG     0xA1
00341 #define M6812_PACN3     0xA2
00342 #define M6812_PACN2     0xA3
00343 #define M6812_PACN1     0xA4
00344 #define M6812_PACN0     0xA5
00345 #define M6812_MCCTL     0xA6
00346 #define M6812_MCFLG     0xA7
00347 #define M6812_ICPAR     0xA8
00348 #define M6812_DLYCT     0xA9
00349 #define M6812_ICOVW     0xAA
00350 #define M6812_ICSYS     0xAB
00351 #define M6812__RESAC    0xAC
00352 #define M6812_TIMTST    0xAD
00353 #define M6812_PORTT     0xAE
00354 #define M6812_DDRT      0xAF
00355 #define M6812_PBCTL     0xB0
00356 #define M6812_PBFLG     0xB1
00357 #define M6812_PA3H      0xB2
00358 #define M6812_PA2H      0xB3
00359 #define M6812_PA1H      0xB4
00360 #define M6812_PA0H      0xB5
00361 #define M6812_MCCNT     0xB6
00362 #define M6812_TC0H      0xB8
00363 #define M6812_TC1H      0xBA
00364 #define M6812_TC2H      0xBC
00365 #define M6812_TC3H      0xBE
00366 
00367 /******** SCI Port (Asynchronous) *******/
00368 
00369 #define M6812_SC0BD     0xC0
00370 #define M6812_SC0BDH    0xC0
00371 #define M6812_SC0BDL    0xC1
00372 
00373 #define M6812_SC0CR1    0xC2
00374 /* Flags in the SC0CR1 */
00375 #define M6812_LOOPS     (byte)(1<<7)    //SCI Loop Mode/Single Wire Mode Enable
00376 #define M6812_WOMS      (byte)(1<<6)    //Wired-Or Mode for Serial Pins
00377 #define M6812_RSRC      (byte)(1<<5)    //Receiver source
00378 #define M6812_M         (byte)(1<<4)    //SCI Character length
00379 #define M6812_WAKE      (byte)(1<<3)    //Wake up method select (0=idle, 1=addr mark)
00380 #define M6812_ILT       (byte)(1<<2)    //Idle Line Type (0=short, 1=long)
00381 #define M6812_PE        (byte)(1<<1)    //Parity Enable
00382 #define M6812_PT        (byte)(1<<0)    //Parity Type (0=even, 1=odd)
00383 
00384 #define M6812_SC0CR2    0xC3
00385 /* Flags in the SC0CR2 */
00386 #define M6812_TIE       (byte)(1<<7)    //Transmit Interrupt enable
00387 #define M6812_TCIE      (byte)(1<<6)    //Transmit Complete Interrupt Enable
00388 #define M6812_RIE       (byte)(1<<5)    //Receive Interrupt Enable
00389 #define M6812_ILIE      (byte)(1<<4)    //Idle Line Interrupt Enable
00390 #define M6812_TE        (byte)(1<<3)    //Transmit Enable
00391 #define M6812_RE        (byte)(1<<2)    //Receive Enable
00392 #define M6812_RWU       (byte)(1<<1)    //Receiver Wake Up
00393 #define M6812_SBK       (byte)(1<<0)    //Send Break
00394 
00395 #define M6812_SC0SR1    0xC4
00396 /* Flags in SC0SR1 */
00397 #define M6812_TDRE      (byte)(1<<7)    //Transmit Data Register Empty
00398 #define M6812_TC        (byte)(1<<6)    //Transmit Complete
00399 #define M6812_RDRF      (byte)(1<<5)    //Receive Data Register Full
00400 #define M6812_IDLE      (byte)(1<<4)    //Idle Line Detect
00401 #define M6812_OR        (byte)(1<<3)    //Overrun Error
00402 #define M6812_NF        (byte)(1<<2)    //Noise Flag
00403 #define M6812_FE        (byte)(1<<1)    //Framing Error
00404 #define M6812_PF        (byte)(1<<0)    //Parity Error flag
00405 
00406 #define M6812_SC0SR2    0xC5
00407 /* Flags in SC0SR2 */
00408 #define M6812_RAF       0x01            //Receiver Active Flag
00409 
00410 #define M6812_SC0DRH    0xC6
00411 #define M6812_SC0DRL    0xC7            //Character received from hardware
00412 #define M6812_SC1BD     0xC8
00413 #define M6812_SC1BDH    0xC8
00414 #define M6812_SC1BDL    0xC9
00415 #define M6812_SC1CR1    0xCA
00416 #define M6812_SC1CR2    0xCB
00417 #define M6812_SC1SR1    0xCC
00418 #define M6812_SC1SR2    0xCD
00419 
00420 #define M6812_SC1DRH    0xCE
00421 /* Flags in SC0DRH */
00422 #define M6812_R8        (byte)(1<<7)    //Receive Bit 8
00423 #define M6812_T8        (byte)(1<<6)    //Transmit bit 8
00424 
00425 #define M6812_SC1DRL    0xCF
00426 
00427 /********* SPI Port (synchronous) *********/
00428 
00429 #define M6812_SP0CR1    0xD0
00430 /* Flags in SP0CR1 */
00431 #define M6812_SPIE      (byte)(1<<7)    //interrupt enable
00432 #define M6812_SPE       (byte)(1<<6)    //SPI enable
00433 #define M6812_SWOM      (byte)(1<<5)    //PortS Wired-OR Mode
00434 #define M6812_MSTR      (byte)(1<<4)    //Master mode select
00435 #define M6812_CPOL      (byte)(1<<3)    //Clock Polarity
00436 #define M6812_CPHA      (byte)(1<<2)    //Clock Phase
00437 #define M6812_SSOE      (byte)(1<<1)    //Slave Select (SS) Output enable
00438 #define M6812_LSBF      (byte)(1<<0)    //LSB first (reverse bits transmitted)
00439 
00440 #define M6812_SP0CR2    0xD1
00441 /* Flags in SP0CR2 */
00442 #define M6812_PUPS      (byte)(1<<3)    //Pullups
00443 #define M6812_RDS       (byte)(1<<2)    //Reduce Drive
00444 #define M6812_SPC0      (byte)1       //Serial Pin Control 0 Bit
00445 
00446 #define M6812_SP0BR     0xD2          //Baud rate, max 7 (31.3kHz)
00447 
00448 #define M6812_SP0SR     0xD3          //SPI Status
00449 /* Flags in SP0SR */
00450 #define M6812_SPIF      (byte)(1<<7)    //interrupt request flag
00451 #define M6812_WCOL      (byte)(1<<6)    //Write collision stat
00452 #define M6812_MODF      (byte)(1<<4)    //Err interrupt stat
00453 
00454 #define M6812__RESD4    0xD4
00455 
00456 #define M6812_SP0DR     0xD5          //Data register for SPI
00457 
00458 #define M6812_PORTS     0xD6
00459 #define M6812_DDRS      0xD7
00460 /* Bit-to-port for PORTS and DDRS */
00461 #define M6812_PORTS_SS   (byte)(1<<7)
00462 #define M6812_PORTS_SCK        (1<<6)
00463 #define M6812_PORTS_MOSI       (1<<5)
00464 #define M6812_PORTS_MISO       (1<<4)
00465 #define M6812_PORTS_TXD1       (1<<3)
00466 #define M6812_PORTS_ADDR1      M6812_PORTS_TXD1
00467 #define M6812_PORTS_RXD1       (1<<2)
00468 #define M6812_PORTS_ADDR0      M6812_PORTS_RXD1
00469 #define M6812_PORTS_TXD0       (1<<1)
00470 #define M6812_PORTS_RXD0       (1<<0)
00471 
00472              /* 0xD8 - 0xDA   Reserved */
00473 
00474 #define M6812_PURDS     0xDB
00475 /* Flags in PURDS */
00476 #define M6812_RDPS2     (byte)(1<<6)    //Reduce Drive for PS7-PS4
00477 #define M6812_RDPS1     (byte)(1<<5)    //                 PS3,PS2
00478 #define M6812_RDPS0     (byte)(1<<4)    //                 PS1,PS0
00479 #define M6812_PUPS2     (byte)(1<<2)    //Pullups for PS7-PS4
00480 #define M6812_PUPS1     (byte)(1<<1)    //            PS3,PS2
00481 #define M6812_PUPS0           1       //            PS1,PS0
00482 
00483              /* 0xDC - 0xDF   Reserved */
00484 #define M6812_SLOW      0xE0
00485              /* 0xE1 - 0xEF   Reserved */
00486 
00487 #define M6812_EEMCR     0xF0
00488 /* Flags in EEMCR */
00489 #define M6812_EESWAI    (1<<2)
00490 #define M6812_PROTLCK   (1<<1)
00491 #define M6812_EERC      (1<<0)
00492 
00493 #define M6812_EEPROT    0xF1        //protect bits for banks of eeprom
00494 /* Blocks to protect */
00495 #define M6812_EEPROT_000      (1<<4)
00496 #define M6812_EEPROT_100      (1<<3)
00497 #define M6812_EEPROT_200      (1<<2)
00498 #define M6812_EEPROT_280      (1<<1)
00499 #define M6812_EEPROT_2C0      (1<<0)
00500 
00501 #define M6812_EETST     0xF2
00502 
00503 #define M6812_EEPROG    0xF3
00504 /* Flags in EEPROG */
00505 #define M6812_BULKP     (byte)(1<<7)
00506 #define M6812_BYTE      (1<<4)
00507 #define M6812_ROW       (1<<3)
00508 #define M6812_ERASE     (1<<2)
00509 #define M6812_EELAT     (1<<1)
00510 #define M6812_EEPGM     (1<<0)
00511 
00512 #define M6812_FEELCK    0xF4
00513 #define M6812_FEEMCR    0xF5
00514 #define M6812_FEETST    0xF6
00515 #define M6812_FEECTL    0xF7
00516              /* 0xF8 - 0xFF   BDLC not present*/
00517 
00518 /********** msCAN Controller Area Network **********/
00519 
00520 #define M6812_CMCR0     0x100       //Module Control Register 0
00521 /* Flags in CMCR0 */
00522 #define M6812_CSWAI     (1<<5)        //Stop in Wait mode
00523 #define M6812_SYNCH     (1<<4)        //Synchronized-to-CAN-bus status
00524 #define M6812_TLNKEN    (1<<3)        //Timer enable flag (to time frame with input capt
00525 #define M6812_SLPAK     (1<<2)        //Sleep Ack flag
00526 #define M6812_SLPRQ     (1<<1)        //Sleep Request for enabling sleep mode
00527 #define M6812_SFTRES    (1<<0)        //Soft-Reset mode. 1=config CAN, 0=active
00528 
00529 #define M6812_CMCR1     0x101       //Module Control Register 1
00530 /* Flags in CMCR1 */
00531 #define M6812_LOOPB     (1<<2)        //loopback for standalone testing
00532 #define M6812_WUPM      (1<<1)        //Wakeup Mode Flag (filter wakeup glitches)
00533 #define M6812_CLKSRC    (1<<0)        //Clock Source 0=EXTALi, 1=2*ECLK
00534 
00535 #define M6812_CBTR0     0x102       //Bus Timing Register
00536 /* Fields in CBTR0 */
00537 #define M6812_POS_SJW       6           //Synch Jump Width
00538 #define M6812_MSK_SJW   (0x3<<M6812_SJW)
00539 #define M6812_MSK_BRP   (0x3F)      //Baudrate prescaler (val 0-63 = div 1-64)
00540 
00541 #define M6812_CBTR1     0x103       //Bus Timing Reg 1
00542 /* Flags/Fields in CBTR1 */
00543 #define M6812_SAMP      (byte)(1<<7) //Samples per bit (1=3samps)
00544 #define M6812_POS_TSEG2  4           //bit offset to TSEG2 bits
00545 #define M6812_MSK_TSEG2  (0x7<<M6812_POS_TSEG2)
00546 #define M6812_MSK_TSEG1  (0xF)
00547 
00548 #define M6812_CRFLG     0x104       //Receiver Flag Register
00549 /* Flags in CRFLG */
00550 #define M6812_WUPIF     (byte)(1<<7)      //Wakeup
00551 #define M6812_RWRNIF    (1<<6)      //Receiver warnning
00552 #define M6812_TWRNIF    (1<<5)      //Transmitter warnning
00553 #define M6812_RERRIF    (1<<4)      //Receiver Error Passive
00554 #define M6812_TERRIF    (1<<3)      //Transmitter Error Passive
00555 #define M6812_BOFFIF    (1<<2)      //Bus-Off
00556 #define M6812_OVRIF     (1<<1)      //Overrun
00557 #define M6812_RXF       (1<<0)      //Receive Buffer Full
00558 #define M6812_RX_ERRMSK (M6812_RWRNIF|M6812_RERRIF|M6812_OVRIF)    //(0x52)
00559 #define M6812_TX_ERRMSK (M6812_TWRNIF|M6812_TERRIF|M6812_BOFFIF)   //(0x2C)
00560 
00561 #define M6812_CRIER     0x105       //Receiver Interrupt Enable Register
00562 /* Flags in CRIER */
00563 #define M6812_WUPIE     (byte)(1<<7)      //Wakeup
00564 #define M6812_RWRNIE    (1<<6)      //Receiver warnning
00565 #define M6812_TWRNIE    (1<<5)      //Transmitter warnning
00566 #define M6812_RERRIE    (1<<4)      //Receiver Error Passive
00567 #define M6812_TERRIE    (1<<3)      //Transmitter Error Passive
00568 #define M6812_BOFFIE    (1<<2)      //Bus-Off
00569 #define M6812_OVRIE     (1<<1)      //Overrun
00570 #define M6812_RXFIE     (1<<0)      //Receive Buffer Full
00571 
00572 #define M6812_CTFLG     0x106       //Transmitter Flg Reg
00573 /* Flags in CTFLG */
00574 #define M6812_ABTAK2    (1<<6)      //set if abort successful
00575 #define M6812_ABTAK1    (1<<5)
00576 #define M6812_ABTAK0    (1<<4)
00577 #define M6812_TXE2      (1<<2)      //ready to send next. Write 1 to clear and send next
00578 #define M6812_TXE1      (1<<1)
00579 #define M6812_TXE0      (1<<0)
00580 
00581 #define M6812_CTCR      0x107       //Transmitter control Reg
00582 /* Flags in CTCR */
00583 #define M6812_ABTRQ2    (1<<6)      //Request abort if hasn't started sending
00584 #define M6812_ABTRQ1    (1<<5)
00585 #define M6812_ABTRQ0    (1<<4)
00586 #define M6812_TXEIE2    (1<<2)      //Transmitter empty IRQ enable
00587 #define M6812_TXEIE1    (1<<1)
00588 #define M6812_TXEIE0    (1<<0)
00589 
00590 #define M6812_CIDAC     0x108       //Identifier acceptance control reg
00591 /* Fields in CIDAC */
00592 #define M6812_POS_IDAM 4           //bit position for IDent Acceptance filter bits
00593 #define M6812_MSK_IDAM  (0x3<<M6812_POS_IDAM)
00594 #define M6812_MSK_IDHIT (0x7)       //bits for IDA Hit. Shows which filter(s) hit
00595 
00596 #define M6812_CRXERR    0x10E       //Receive err count
00597 #define M6812_CTXERR    0x10F       //Transmit err count
00598 
00599 #define M6812_CIDAR0    0x110       //ID Acceptance Register (32 bits by 2 banks)
00600 #define M6812_CIDAR2    0x112
00601 #define M6812_CIDMR0    0x114       //Mask IDA
00602 #define M6812_CIDMR2    0x116
00603 #define M6812_CIDAR4    0x118
00604 #define M6812_CIDAR6    0x11A
00605 #define M6812_CIDMR4    0x11C
00606 #define M6812_CIDMR6    0x11E
00607 
00608 #define M6812_PCTLCAN   0x13D       //pin control
00609 /* Flags in PCTLCAN */
00610 #define M6812_PUECAN    (1<<1)      //Pullup ena
00611 #define M6812_RDPCAN    (1<<0)      //Reduced Drive ena
00612 
00613 #define M6812_PORTCAN   0x13E       //data i/o, 1=TxCAN 0=RxCAN
00614 #define M6812_DDRCAN    0x13F       //data direction for each CAN io
00615 
00616 /* CAN buffers */
00617 #define M6812_RXFG      0x140       //Receive buffer     (CAN message buffers)
00618 #define M6812_TX0       0x150       //Transmit buffer 0
00619 #define M6812_TX1       0x160       //Transmit buffer 1
00620 #define M6812_TX2       0x170       //Transmit buffer 2
00621 /* Offsets of CAN message buffers */
00622 #define M6812_CAN_IDR0   0x0        //Destination/type of message
00623 #define M6812_CAN_IDR2   0x2
00624 #define M6812_CAN_DATA   0x4        //up to 8 data bytes (0x4-0xB)
00625 #define M6812_CAN_LEN    0xC        //number of data bytes
00626 #define M6812_CAN_PRIO   0xD        //not applicable for Rx buffer
00627 /* Fields/Flags in (word) IDR0-1 */
00628 #define M6812_CAN_POS_ID  5
00629 #define M6812_CAN_MSK_ID  ((word)0xFFE0)  //all bits for standard ID
00630 #define M6812_CAN_RTR     ((word)0x0010)  //std RTR (always 1 in extended)
00631 #define M6812_CAN_IDE     ((word)0x0008)  //1=extended ID
00632 /* Flag in (word) IDR2-3 */
00633 #define M6812_CAN_XRTR    ((word)0x0001)  //extened RTR
00634 
00635 /**************************************************************/
00636 
00637 /* Default SCI port is SC0. (SC1 is not even implimented on our chip) */
00638 #define M6812_SCBD     M6812_SC0BD
00639 #define M6812_SCCR1    M6812_SC0CR1
00640 #define M6812_SCCR2    M6812_SC0CR2
00641 #define M6812_SCSR1    M6812_SC0SR1
00642 #define M6812_SCSR2    M6812_SC0SR2
00643 #define M6812_SCDRH    M6812_SC0DRH
00644 #define M6812_SCDRL    M6812_SC0DRL
00645 #define M6812_SCDR     M6812_SC0DRL
00646 
00647 /* default input register for AD */
00648 #define M6812_PORTAD   M6812_PORTAD0
00649 
00650 /* Ports with common name and function between hc11/hc12 */
00651 #if 0
00652 #define M6811_PORTA        M6812_PORTA   //Port A register
00653 #define M6811_PORTB        M6812_PORTB   //Port B register
00654 #endif
00655 #define M6811_DDRA         M6812_DDRA    //Data Direction Port A
00656 #define M6811_DDRB         M6812_DDRB    //Data Direction Port A
00657 
00658 /* Bit-to-port for PORTS and DDRS, common name between hc11/hc12 */
00659 #define PORTS_SS      M6812_PORTS_SS
00660 #define PORTS_SCK     M6812_PORTS_SCK
00661 #define PORTS_MOSI    M6812_PORTS_MOSI
00662 #define PORTS_MISO    M6812_PORTS_MISO
00663 #define PORTS_TXD1    M6812_PORTS_TXD1
00664 #define PORTS_RXD1    M6812_PORTS_RXD1
00665 #define PORTS_ADDR1   M6812_PORTS_TXD1
00666 #define PORTS_ADDR0   M6812_PORTS_RXD1
00667 #define PORTS_TXD0    M6812_PORTS_TXD0
00668 #define PORTS_RXD0    M6812_PORTS_RXD0
00669 
00670 
00671 /* The I/O registers are represented by a volatile array.
00672    Address if fixed at link time.  */
00673 extern volatile unsigned char _io_ports[];
00674 
00675 #define M6811_SPSR M6812_SP0SR
00676 #define M6811_SPDR M6812_SP0DR
00677 #define M6811_SPCR M6812_SP0CR1
00678 #define M6811_SPIF M6812_SPIF
00679 #define M6811_SPE  M6812_SPE
00680 #define M6811_DDRD M6812_DDRS
00681 
00682 #endif /* _M68HC11_PORTS_DEF_H */
00683